Design of an Analog to Digital Converter for Analog in Memory Computing

In this thesis, the design and simulations in CAD environment of an Analog to Digital Converter for an Analog in Memory Computing (AiMC) test chip were presented. The AiMC circuit has the goal of computing efficiently, in terms of both area and power consumption, a Multiply and Accumulate operation (MAC) which is the fundamental operation exploited by different deep learning algorithms. MAC operations are mainly used to solve different processing steps in Convolutional Neural Networks, i.e. systems that are able to recognize image patterns and are used today in a variety of applications, from computer vision, autonomous driving, medical diagnostics, etc. The test chip relies on a PCM memory array to perform the products between the weights of a neural network, stored as conductance value in each PCM cell, and the inputs, provided as a voltage pulse across each Word Line (row) of the memory matrix. The current generated by the activated cells is then naturally summed, thanks to the array topology, along each Bit Line (column) providing the result of the MAC operations. Due to the challenge related to area occupation and speed, the implementation of standard ADC topologies (e.g. Flash, SAR, Sigma-delta) was not possible. The proposed converter architecture relies on a Charge Controlled Oscillator (CCO) to count the charge packets that represent the result of the aforementioned MAC operation. Indeed, the charges are obtained as the integral of a scaled replica of the Bit Line current that is injected into a capacitive load to be converted into a square-wave whose frequency is proportional to the value of the current being integrated. The digital output value is obtained through a ripple counter driven by the square-wave signal generated by the CCO. The ADC is able to provide the digital output as soon as the integration of a Bit Line current is finished without adding any overhead time making it very promising in term of speed.