An automatic setup for gate current measurement in 28 nm NMOS transistors

Over the past three decades, the Moore’s law-predicted exponential growth of complementary metal-oxide-semiconductor (CMOS) technology has been successfully proved. In order to meet the requirements on speed, complexity, circuit density, and power consumption of advanced high performance digital applications, CMOS technologies have been continuously downscaled. The introduction of nanoscale (sub-100nm) CMOS technologies has improved digital performance even further, but it has also presented several new challenges for analog designers. Actually, CMOS scaling-down has various advantages for digital circuits, including increased speed, decreased power consumption, and high integration, and complexity level. Scaling of physical (length, oxide thickness, etc.) and electrical (supply voltage) properties poses problems including reduced intrinsic DC gain and less dynamic range, operating point concerns and more parameter variability, making it difficult to achieve the high performance standards required to handle these problems at various design stages. Despite this, there are specific situations when designing a circuit with sub-nm technologies is required. For instance, the read-out component in systems that use mixed signals must function well at high frequencies, making the adoption of deep submicron technology necessary. In high-energy physics experiments, read-out circuits are subjected to extremely high radiation levels with a resulting performance deterioration. Smaller devices show less radiation damage because gate oxide volume is inversely correlated with radiation tolerance. This thesis explores the features of a 28nm CMOS technology. In particular, the objective of this work is to develop an automatic setup that measures the gate current in 28 nm NMOS transistors to perform online measurements during irradiation and to speed up measurements on a large set of devices in different operating conditions, therefore accumulating a statistically significant amount of data in order to overcome the significant scaling issues and provide the required performance.

Sistema automatico per la misura della corrente di gate in transistori NMOS da 28 nm