Nowadays, electro-optical communications keep on developing more challenging requests, especially when it comes to speed and energy efficiency. As any electrical circuit would eat a certain amount of power and produce a result in a variable time, it’s crucial to quantify and minimize these two specifications in every application. It becomes even more important in transceivers. They implement the wire enabling people to connect, store and access data, which are everyday activities, necessary for most jobs, errands and leisure and this need appeared even more evident with the advent of 5G and Internet of Things (IoT). Being SAR ADC a capital part of its functioning -and the key analog block in receivers- the question is how to optimize it. The answer is to individuate the bottleneck, namely the comparator inside the SAR, and try to bypass it. In particular, comparators set some limits on speed, accuracy, power and noise. These quantities are in a trade-off, hence the search for the best topology is still open. This master thesis will deal with the most popular and performing architectures, seeking the most efficient solution.
Nowadays, electro-optical communications keep on developing more challenging requests, especially when it comes to speed and energy efficiency. As any electrical circuit would eat a certain amount of power and produce a result in a variable time, it’s crucial to quantify and minimize these two specifications in every application. It becomes even more important in transceivers. They implement the wire enabling people to connect, store and access data, which are everyday activities, necessary for most jobs, errands and leisure and this need appeared even more evident with the advent of 5G and Internet of Things (IoT). Being SAR ADC a capital part of its functioning -and the key analog block in receivers- the question is how to optimize it. The answer is to individuate the bottleneck, namely the comparator inside the SAR, and try to bypass it. In particular, comparators set some limits on speed, accuracy, power and noise. These quantities are in a trade-off, hence the search for the best topology is still open. This master thesis will deal with the most popular and performing architectures, seeking the most efficient solution.
Analysis of a low power comparator with a dynamic bias in 5nm FinFet technology
MARAZZI, VALENTINA
2021/2022
Abstract
Nowadays, electro-optical communications keep on developing more challenging requests, especially when it comes to speed and energy efficiency. As any electrical circuit would eat a certain amount of power and produce a result in a variable time, it’s crucial to quantify and minimize these two specifications in every application. It becomes even more important in transceivers. They implement the wire enabling people to connect, store and access data, which are everyday activities, necessary for most jobs, errands and leisure and this need appeared even more evident with the advent of 5G and Internet of Things (IoT). Being SAR ADC a capital part of its functioning -and the key analog block in receivers- the question is how to optimize it. The answer is to individuate the bottleneck, namely the comparator inside the SAR, and try to bypass it. In particular, comparators set some limits on speed, accuracy, power and noise. These quantities are in a trade-off, hence the search for the best topology is still open. This master thesis will deal with the most popular and performing architectures, seeking the most efficient solution.È consentito all'utente scaricare e condividere i documenti disponibili a testo pieno in UNITESI UNIPV nel rispetto della licenza Creative Commons del tipo CC BY NC ND.
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https://hdl.handle.net/20.500.14239/15336