In this thesis we will deal with the analysis of different capacitive coupled level shifter architectures to be used for the realization of gate drivers for the control of electric motors, with particular interest in applications in the 250V/300V voltage range. Nowadays the consumption of electricity is constantly increasing, more than half of the electricity is used to power electric motors. In order to be able to work more efficiently from an energy point of view, a motor needs appropriate control. For this reason, the so-called inverter topology is usually used. This control method is based on the use of high-voltage switches arranged in an architecture called inverter-leg. These switches are driven by a microcontroller that, according to the different operating speeds of the motor, decides to turn these elements on or off, in order to control, for example, the speed of rotation of the motor. This, in principle, allows the system to consume only the necessary power at a given moment of time. In this context, the gate driver is the interface circuit (between the low-voltage domain of the microcontroller and the high-voltage domain of the switches) that is responsible for generating and managing the voltage levels that are required for motor control. As anticipated, in this thesis we will focus on the level shifter, a functional sub-block of the gate driver, which serves to translate into the high-voltage domain the requests to turn on and off the high side switch (i.e. the switch that connects the supply voltage to the motor). In particular, we will consider the problems related to the monolithic implementation of the level shifter (i.e. the monolithic integration of the parts of low side, low voltage, and high side, high voltage). Traditionally, a monolithic level shifter has been implemented using Double-Diffused MOSFET (DMOS) devices as communication elements between low side and high side. This thesis work will mainly focus on an alternative implementation of level shifter in which the communication elements are not DMOS devices but are high-voltage capacitors. There is currently a strong interest in the development of this new level shifter topology, given the considerable advantages it has over the traditional approach. These advantages include, for example, better isolation between the two domains and the possibility of reducing the propagation delay of the signals to be transmitted. Several level shifter architectures based on capacitive coupling were analyzed and designed. The design was carried out using a SOI (Silicon on Insulator) technology provided by Infineon and was guided by some reference specifications. At the end of this project, it was possible to obtain a comparison between the different architectures considered with the aim of identifying the most suitable structure to guarantee the required performance in the most effective way, not only in terms of power consumption but also in robustness. This architecture will then be realized on silicon through a special demonstrator (test-chip) and, therefore, experimentally characterized in order to evaluate the actual functionality of the proposed system.
Analisi e Progettazione di Architetture Level Shifter ad Accoppiamento Capacitivo per Applicazioni PWM di Controllo Motore. In questa tesi ci occuperemo dell'analisi di diverse architetture di level shifter ad accoppiamento capacitivo da utilizzare per la realizzazione di gate driver per il controllo di motori elettrici, con particolare interesse ad applicazioni nel range di tensione 250V/300V. Oggigiorno il consumo di energia elettrica è in continuo aumento, più della metà dell'energia elettrica viene utilizzata per alimentare motori elettrici. Per poter lavorare in modo più efficiente dal punto energetico un motore ha bisogno di un opportuno controllo. Per questo motivo viene solitamente utilizzata la topologia detta ad inverter. Questo metodo di controllo si basa sull'utilizzo di interruttori ad alta tensione arrangiati in una architettura detta appunto inverter-leg. Questi interruttori sono pilotati da un microcontrollore che in base ai diversi regimi di funzionamento del motore decide di accendere o spegnere questi elementi, in modo da controllare, ad esempio, la velocità di rotazione del motore. Questo, in linea di principio permette al sistema di consumare esclusivamente la potenza necessaria in un determinato istante di tempo. In questo contesto, il gate driver è il circuito di interfaccia (tra il dominio a bassa tensione del microcontrollore e il dominio ad alta tensione degli interruttori) che si occupa di generare e gestire i livelli di tensione che sono richiesti per il controllo del motore. Come anticipato, in questa tesi andremo a focalizzare l'attenzione sul level shifter, un sotto blocco funzionale del gate driver, che serve a traslare nel dominio ad alta tensione le richieste di accensione e spegnimento dell'interruttore high side (ovvero l'interrutore che collega la tensione di alimentazione al motore). In particolare, andremo a considerare le problematiche relative all'implementazione monolitica del level shifter (ovvero l'integrazione monolitica delle parti di low side, a bassa tensione, e high side, ad alta tensione). Tradizionalmente, un level shifter monolitico viene implementato utilizzando dispositivi DMOS (Double-Diffused MOSFET) come elementi di comunicazione tra low side} e high side. Questo lavoro di tesi si focalizzerà principalmente su un'implementazione alternativa di level shifter nella quale gli elementi di comunicazione non sono dispositivi DMOS ma sono capacità ad alta tensione. Attualmente si ha un forte interesse nello sviluppo di questa nuova topologia di level shifter, dati i considerevoli vantaggi che essa presenta rispetto all'approccio tradizionale. Fra questi vantaggi si ha ad esempio un migliore isolamento tra i due domini e la possibilità di ridurre il ritardo di propagazione dei segnali da trasmettere. Sono state analizzate e progettate diverse architetture di level shifter basate su accoppiamento capacitivo. La progettazione è stata effettuata utilizzando una tecnologia SOI (Silicon on Insulator) messa a disposizione da Infineon ed è stata guidata da alcune specifiche di riferimento. Alla fine di questo progetto è stato possibile ottenere un confronto tra le diverse architetture considerate con lo scopo di individuare la struttura più adatta a garantire le prestazioni richieste nel modo più efficace, non solamente in termini di consumo di potenza ma anche in robustezza. Questa architettura sarà successivamente realizzata su silicio tramite un apposito dimostratore (test-chip) e, quindi, caratterizzata sperimentalmente al fine di valutare l'effettiva funzionalità del sistema proposto.
Analysis and Design of Capacitively Coupled Level Shifter Architectures for Motor Control PWM Applications
CANATO, LUCA
2021/2022
Abstract
In this thesis we will deal with the analysis of different capacitive coupled level shifter architectures to be used for the realization of gate drivers for the control of electric motors, with particular interest in applications in the 250V/300V voltage range. Nowadays the consumption of electricity is constantly increasing, more than half of the electricity is used to power electric motors. In order to be able to work more efficiently from an energy point of view, a motor needs appropriate control. For this reason, the so-called inverter topology is usually used. This control method is based on the use of high-voltage switches arranged in an architecture called inverter-leg. These switches are driven by a microcontroller that, according to the different operating speeds of the motor, decides to turn these elements on or off, in order to control, for example, the speed of rotation of the motor. This, in principle, allows the system to consume only the necessary power at a given moment of time. In this context, the gate driver is the interface circuit (between the low-voltage domain of the microcontroller and the high-voltage domain of the switches) that is responsible for generating and managing the voltage levels that are required for motor control. As anticipated, in this thesis we will focus on the level shifter, a functional sub-block of the gate driver, which serves to translate into the high-voltage domain the requests to turn on and off the high side switch (i.e. the switch that connects the supply voltage to the motor). In particular, we will consider the problems related to the monolithic implementation of the level shifter (i.e. the monolithic integration of the parts of low side, low voltage, and high side, high voltage). Traditionally, a monolithic level shifter has been implemented using Double-Diffused MOSFET (DMOS) devices as communication elements between low side and high side. This thesis work will mainly focus on an alternative implementation of level shifter in which the communication elements are not DMOS devices but are high-voltage capacitors. There is currently a strong interest in the development of this new level shifter topology, given the considerable advantages it has over the traditional approach. These advantages include, for example, better isolation between the two domains and the possibility of reducing the propagation delay of the signals to be transmitted. Several level shifter architectures based on capacitive coupling were analyzed and designed. The design was carried out using a SOI (Silicon on Insulator) technology provided by Infineon and was guided by some reference specifications. At the end of this project, it was possible to obtain a comparison between the different architectures considered with the aim of identifying the most suitable structure to guarantee the required performance in the most effective way, not only in terms of power consumption but also in robustness. This architecture will then be realized on silicon through a special demonstrator (test-chip) and, therefore, experimentally characterized in order to evaluate the actual functionality of the proposed system.È consentito all'utente scaricare e condividere i documenti disponibili a testo pieno in UNITESI UNIPV nel rispetto della licenza Creative Commons del tipo CC BY NC ND.
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https://hdl.handle.net/20.500.14239/15745