20Gb/s Adaptive Linear Equalizer in 28nm CMOS: Analysis and Measurement Results

The never ending growth of internet traffic pushes continuously for higher speed in wireline links adopted in networking equipment. Channel loss is a primary limitation and to increase speed, more complex equalization techniques need to be investigated. In this work, a continuous-time linear equalizer with a transversal architecture, build up by tapping the cascade of first-order high-pass filters, is explained. The architecture, previously implemented in 28nm CMOS, leads to high flexibility and enables optimal adaptation to channels variations and/or different channel profiles. The thesis starts by presenting the block diagram of the architecture and circuit implementations of the main building blocks. In the last part, extensive experimental results, both in frequency and time domain are proposed, showing good equalization results at data/rate from 10 to 20Gb/s over backplane channels with up to 20dB loss.