Analysis and Design of a 56 Gb/s PAM4 Un-Clocked Decision Feedback Equalizer in 16nm FinFET

With an increasing number of user who accesses internet everyday, the data traffic inevitably expands. Furthermore, as CMOS technologies are scaled down, the density of digital computing rise, the total system bandwidth must be increased in order to cover all of the available computing power. Therefore huge demand on high speed data communication over optical fibers, backplane channels, intra-chip, chip to chip, rack to rack and system to system is created. In order to handle this demand, new standards with 56 Gb/s such as OIF CEI-56G-LR, CEI-56G-XSR and multilevel signalling are under investigation. The main problem which is the variation in channel response becomes more severe with increasing data rate. Channel loss cause Inter Symbol Interference (ISI) which decreases Bit Error Rate (BER). The problem can be solved by adding equalizer circuit in receiver (RX) and/or transmitter (TX). Continuous time linear equalizer can be used to compensate the channel losses however they amplify high frequency noise and cross talk. In order to adapt different channels, backplane topologies and other variables, adaptive equalizers are used to compensate losses and to extend maximum bandwidth. Traditional discrete time (DT) decision feedback equalizers can be used to remove the post cursor ISI, however with increasing speed, the accuracy of timing recovery brings additional challenges. Half-rate clock DFEs by loop-unrolling are widely applied to avoid feeding back the decided bit within a 1-bit (UI) time, but the alternated eye opening that is created requires an increased circuit complexity to obtain the maximum accuracy in timing recovery. In order to eliminate the stringent time constraint for traditional DFEs and also to relax bandwidth requirement for high data rate, in this work, it is aimed to analyse and design PAM4 Decision Feedback Equalizer without using clock network. Thesis is organized as follows. First chapter is an introduction to the high speed communication system. In second chapter, focused on description of wire-line serial link with considering typical model of a backplane communication channel and also different type of equalizers are discussed. In chapter three, the system of "A 56 Gb/s PAM-4 UN-CLOCKED DECISION FEEDBACK EQUALIZER IN 16nm FinFET" is studied and analysed. In fourth chapter, fundamental building blocks are explained and finally simulation result are shown.