Repetitive short-circuit and repetitive avalanche tests among different Silicon Carbide power MOSFETs

Ensuring the reliability of Silicon Carbide Metal-Oxide-Semiconductor Field-Effect Transistors (SiC MOSFETs) under fault operating conditions is essential to enable the transition from silicon-based (Si-based) to wide bandgap-based power conversion systems, specially under harsh operating conditions such as overcurrents and overvoltages. This reliability is critical to meet long-term application requirements. SiC MOSFETs ability to withstand repetitive short-circuit (RSC) and repetitive avalanche (RA) is a key factor in their overall ruggedness against extreme conditions. This thesis aims to provide an in-depth and comprehensive investigation into the RSC and RA ruggedness of the three commercially available 1.2 kV Silicon Carbide (SiC) power MOSFET Gate channel designs: Planar, Symmetrical Trench and Asymmetrical Trench. The study analyzes samples from five different manufacturers. Fifteen samples were analyzed for RSC tests, while ten samples were analyzed for RA tests. Samples were first analyzed in depth, in order to obtain details such as the active area (A.A.) and the Gate Oxide thickness of them, crucial for the necessary computations related to energy density for both tests performed. Subsequently, for both tests performed, devices under test (DUTs) were stressed with similar short-circuit (SC) and avalanche (AV) energy density. Electrical parameters such as VGS, VDS and IDS were monitored over 1000 SC and AV cycles applied. After the stresses, DUTs were characterized with a curve tracer and a few failed samples were analyzed in depth to localize via Photon Emission Microscopy (PEM) and understand the type of failure via Focused Ion Beam (FIB) method. Key findings revealed that Planar Gate structures are less robust compared to Trench counterparts, with Gate Oxide thickness playing a critical role in cycle robustness. Devices failure occurs within the Gate Oxide, and it is caused by high temperatures generated by the significant energy dissipation per unit-channel-width. This issue is worsened by the poor thermal dissipation from the Planar Gate to the chip’s top-side metallization. Symmetrical Trench Gate designs struggled with AV events due to higher electric field stress at the trench bottom. Only Trench designs demonstrated ruggedness against RSC, while both Asymmetrical Trench and Planar designs showed ruggedness against RA. Only the Asymmetrical Trench Gate channel structure proved robust against both RSC and RA, highlighting its importance for developing reliable wide bandgap-based power conversion systems.