This thesis presents the design of a very low current DAC for current mode ADC applications. This thesis will propose a new method for designing an 8-bit current steering DAC which has been employed in an 8-bit successive approximation (SAR) ADC. The novel design exploits the exponential relationship between control voltage and output current in MOS transistors operating in weak inversion. All the analog components are designed at circuit level with 0.18 μm CMOS technology and digital components are implemented using Verilog-A in Cadence. The supply voltage used in this project is 1.8 V and the ADC has a sampling frequency of 10 kHz with an input current range from 0 nA to 800 nA. The simulated INL and DNL are between -1.75 ~ +2.25 LSB and -1 ~ +1.75 LSB, respectively.
Progettazione di un DAC a Bassa-Corrente per Applicazioni ADC
Design of a Very-Low-Current DAC for Current-Mode ADC Applications
ABUZARIFA, YASER
2019/2020
Abstract
This thesis presents the design of a very low current DAC for current mode ADC applications. This thesis will propose a new method for designing an 8-bit current steering DAC which has been employed in an 8-bit successive approximation (SAR) ADC. The novel design exploits the exponential relationship between control voltage and output current in MOS transistors operating in weak inversion. All the analog components are designed at circuit level with 0.18 μm CMOS technology and digital components are implemented using Verilog-A in Cadence. The supply voltage used in this project is 1.8 V and the ADC has a sampling frequency of 10 kHz with an input current range from 0 nA to 800 nA. The simulated INL and DNL are between -1.75 ~ +2.25 LSB and -1 ~ +1.75 LSB, respectively.È consentito all'utente scaricare e condividere i documenti disponibili a testo pieno in UNITESI UNIPV nel rispetto della licenza Creative Commons del tipo CC BY NC ND.
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https://hdl.handle.net/20.500.14239/12766