The trend, in the microelectronic field, towards an increasing miniaturization of the devices used for the fabrication of integrated circuits is enabling a progressive increase of the functionalities present in a single chip yielding significant advantages in terms of performance, reliability and power consumption of the relevant circuits. In this framework, modern technologies can also offer interesting solutions for parallel processing of two-dimensional structures. In this respect, integrated circuits capable of working with matrix structures with binary outputs (i.e., elementary cell structures having a logic 1 or 0 output), able of processing information on the number of cells which take a logical 1 value, is of increasing interest in different fields of application. These include, for example, matrices of SPAD (Single Photon Avalanche Diode) sensors for positron emission tomography (PET), remote sensing (LIDAR) or calorimetry applications in high energy physics experiments. This thesis work concerns the analysis and design of a digital integrated circuit (called parallel counter) in a 110 nm CMOS technology, able to implement the mentioned feature. Indeed, from N binary inputs of equal weight, the parallel counter aims at generating a final binary word containing the information on the number of 1’s among the N inputs. Starting from the implementation of parallel multipliers and the available literature on parallel counters, the analysis carried out on the architecture of the parallel counter has been focused on the search for an optimum in terms of processing speed and area occupation and it has been oriented to the analysis of the interconnections between the elementary cells of the counter. This made it possible to develop an algorithm which was useful for the design of the counter and the identification of the necessary requirements for the elementary cells used for its implementation (i.e., full adders). This was followed by the design and the layout of the elementary cells and the design of the counter based on the algorithm. Compliance with the specifications was verified through simulations performed, at the schematic and post-layout level on the elementary cell and on the entire parallel counter.
Analisi e progettazione di un contatore parallelo in tecnologia CMOS 110 nm. La tendenza, in ambito microelettronico, verso una crescente miniaturizzazione dei dispositivi impiegati nella realizzazione di circuiti integrati permette un incremento progressivo delle funzionalità presenti nei singoli chip e significativi vantaggi in termini di prestazioni, affidabilità e consumo di potenza dei relativi circuiti. In questo contesto, le moderne tecnologie possono offrire soluzioni interessanti anche per l’elaborazione parallela di strutture bidimensionali. Al riguardo, circuiti integrati in grado di lavorare con strutture matriciali ad uscite binarie (vale a dire, strutture di elementi unitari ad uscita binaria 1 o 0), in grado di elaborare l’informazione sul numero di celle aventi valore logico 1, risultano di sempre maggior interesse in diversi campi applicativi. Tra queste vanno menzionate, ad esempio, matrici di sensori SPAD (Single Photon Avalanche Diode) per la tomografia ad emissione di positroni (PET), per il telerilevamento (LIDAR) o per applicazioni di calorimetria in fisica delle alte energie. Il presente lavoro di tesi riguarda l’analisi e la progettazione di un circuito digitale integrato (chiamato contatore parallelo), in tecnologia CMOS 110 nm, in grado di implementare la funzionalità citata. Pertanto, a partire da N ingressi binari di ugual peso, il contatore parallelo ha come obiettivo l’elaborazione di una parola binaria finale contenente l’informazione sul numero di bit a 1 tra gli N ingressi. A partire dall’implementazione dei moltiplicatori paralleli e dalla letteratura disponibile sui contatori paralleli, l’analisi svolta sull’architettura del contatore parallelo si è focalizzata sulla ricerca di un ottimo in termini di velocità di elaborazione ed occupazione d’area e sull’analisi delle interconnessioni tra le celle elementari del contatore. Questo ha portato allo sviluppo di un algoritmo utile alla progettazione del contatore e alla identificazione dei requisiti necessari per le celle elementari utilizzate per la sua realizzazione (ovvero, dei full adder). A questo ha fatto seguito la progettazione e il layout delle celle elementari e la progettazione del contatore basata sull’algoritmo sviluppato. Simulazioni, a livello di schematico e post-layout, sulla singola cella e sul contatore parallelo, hanno permesso la verifica delle prestazioni richieste, a sostegno dell’analisi sviluppata al riguardo.
Analysis and design of a parallel counter in 110 nm CMOS technology
GIROLETTI, SIMONE
2020/2021
Abstract
The trend, in the microelectronic field, towards an increasing miniaturization of the devices used for the fabrication of integrated circuits is enabling a progressive increase of the functionalities present in a single chip yielding significant advantages in terms of performance, reliability and power consumption of the relevant circuits. In this framework, modern technologies can also offer interesting solutions for parallel processing of two-dimensional structures. In this respect, integrated circuits capable of working with matrix structures with binary outputs (i.e., elementary cell structures having a logic 1 or 0 output), able of processing information on the number of cells which take a logical 1 value, is of increasing interest in different fields of application. These include, for example, matrices of SPAD (Single Photon Avalanche Diode) sensors for positron emission tomography (PET), remote sensing (LIDAR) or calorimetry applications in high energy physics experiments. This thesis work concerns the analysis and design of a digital integrated circuit (called parallel counter) in a 110 nm CMOS technology, able to implement the mentioned feature. Indeed, from N binary inputs of equal weight, the parallel counter aims at generating a final binary word containing the information on the number of 1’s among the N inputs. Starting from the implementation of parallel multipliers and the available literature on parallel counters, the analysis carried out on the architecture of the parallel counter has been focused on the search for an optimum in terms of processing speed and area occupation and it has been oriented to the analysis of the interconnections between the elementary cells of the counter. This made it possible to develop an algorithm which was useful for the design of the counter and the identification of the necessary requirements for the elementary cells used for its implementation (i.e., full adders). This was followed by the design and the layout of the elementary cells and the design of the counter based on the algorithm. Compliance with the specifications was verified through simulations performed, at the schematic and post-layout level on the elementary cell and on the entire parallel counter.È consentito all'utente scaricare e condividere i documenti disponibili a testo pieno in UNITESI UNIPV nel rispetto della licenza Creative Commons del tipo CC BY NC ND.
Per maggiori informazioni e per verifiche sull'eventuale disponibilità del file scrivere a: unitesi@unipv.it.
https://hdl.handle.net/20.500.14239/13863