The precise measurement of time intervals is essential across various fields, including industrial applications, laboratory electronic instrumentation and particle physics. Many of these applications demand devices that offer high performance in terms of resolution, power efficiency, ompactness and linearity. A promising solution to meet these stringent requirements is the use of integrated circuits known as Time-to-Digital Converters (TDCs), which convert the time interval between two events into a digital word for subsequent processing by digital logic circuits. This thesis focuses on the design and implementation of ring oscillator based Time-To-Digital Converter (TDC) , using a 110 nm CMOS technology. The primary objective is to enable the TDC to operate within a matrix of Single Photon Avalanche Diode (SPAD) sensors, achieving particle arrival time detection on the matrix with a resolution of less than 100 ps. Furthermore, this work examines two distinct control systems for the oscillator: a voltage-controlled system and a current-controlled system. Attention was paid during the layout phase to ensure that the TDC was designed to be fully compatible with standard digital logic. This compatibility is achieved by constructing the building blocks of the TDC using the same basic structure as the standard cells available in the technology library, thereby facilitating integration into more complex systems.
The precise measurement of time intervals is essential across various fields, including industrial applications, laboratory electronic instrumentation and particle physics. Many of these applications demand devices that offer high performance in terms of resolution, power efficiency, ompactness and linearity. A promising solution to meet these stringent requirements is the use of integrated circuits known as Time-to-Digital Converters (TDCs), which convert the time interval between two events into a digital word for subsequent processing by digital logic circuits. This thesis focuses on the design and implementation of ring oscillator based Time-To-Digital Converter (TDC) , using a 110 nm CMOS technology. The primary objective is to enable the TDC to operate within a matrix of Single Photon Avalanche Diode (SPAD) sensors, achieving particle arrival time detection on the matrix with a resolution of less than 100 ps. Furthermore, this work examines two distinct control systems for the oscillator: a voltage-controlled system and a current-controlled system. Attention was paid during the layout phase to ensure that the TDC was designed to be fully compatible with standard digital logic. This compatibility is achieved by constructing the building blocks of the TDC using the same basic structure as the standard cells available in the technology library, thereby facilitating integration into more complex systems.
A Sub 100-ps LSB Pseudo-differential Ring Oscillator Based Time-to-Digital Converter in 110 nm CMOS
FLORIS, TOMMASO MARIA
2023/2024
Abstract
The precise measurement of time intervals is essential across various fields, including industrial applications, laboratory electronic instrumentation and particle physics. Many of these applications demand devices that offer high performance in terms of resolution, power efficiency, ompactness and linearity. A promising solution to meet these stringent requirements is the use of integrated circuits known as Time-to-Digital Converters (TDCs), which convert the time interval between two events into a digital word for subsequent processing by digital logic circuits. This thesis focuses on the design and implementation of ring oscillator based Time-To-Digital Converter (TDC) , using a 110 nm CMOS technology. The primary objective is to enable the TDC to operate within a matrix of Single Photon Avalanche Diode (SPAD) sensors, achieving particle arrival time detection on the matrix with a resolution of less than 100 ps. Furthermore, this work examines two distinct control systems for the oscillator: a voltage-controlled system and a current-controlled system. Attention was paid during the layout phase to ensure that the TDC was designed to be fully compatible with standard digital logic. This compatibility is achieved by constructing the building blocks of the TDC using the same basic structure as the standard cells available in the technology library, thereby facilitating integration into more complex systems.| File | Dimensione | Formato | |
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https://hdl.handle.net/20.500.14239/33286