A 12-bit 1-MS/s 2-bit/cycle Asynchronous SAR ADC for MEMS Applications

This thesis, carried out in collaboration with TDK InvenSense, presents the design of an asynchronous 2-bit-per-cycle Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). By integrating an asynchronous control scheme with a multi-level architecture, the design achieves a 12-bit resolution. Tailored for integration into MEMS-based inertial sensors, the ADC operates at a 1.8-V supply using a 180-nm CMOS technology. Leveraging the inherent advantages of a charge redistribution SAR and a capacitive Digital-to-Analog Converter (CDAC), the design achieves low power consumption and a compact footprint, making it well-suited for power-sensitive applications.