A High Precision Hybrid Σ∆ ADC for Industry 4.0 Applications

This thesis, conducted in collaboration with NXP Semiconductors N.V., presents a study of a Sigma-Delta Analog-to-Digital Converter (ADC). To achieve an optimal compromise between area and power consumption, a hybrid topology is employed, combining a continuous-time input stage with discrete-time following stages. This architecture allows for inherent filtering and improved drivability offered by continuous-time systems, while retaining the benefits of discrete-time integration. A key innovation of this work is the implementation of op-amp slicing, where a single operational amplifier is shared between multiple integrator stages. This reduces the number of amplifiers required, leading to a more compact and power-efficient design, without compromising the performance of a traditional multi-op-amp system. The proposed converter is a third-order Sigma-Delta modulator, designed to be integrated within an Analog Front-End (AFE) circuit for Industry 4.0 applications. The design achieves a resolution of 19 bits, operating with a 3.3-V supply voltage.