A 10GHz Phase-Rotator-Based Fractional Frequency Divider

As high-speed serial links and radio-frequency front-ends move toward GHz operation, clock generators must provide high frequency, wide tuning range, and low phase noise. Conventional LC VCOs offer excellent phase-noise performance but suffer from reduced quality factor when extended to wide tuning ranges. Multi-VCO solutions address this limitation at the cost of increased area, power, and calibration complexity. This thesis proposes a phase-rotator-based frequency divider as a range-extending alternative. A multi-phase delay line, calibrated by a delay-locked loop (DLL), generates accurately spaced clock phases, which are selected by a multiplexer to realise fractional division ratios. The architecture is implemented mainly using standard CMOS digital logic, improving portability and reuse across technology nodes. The design is implemented in a 2 nm CMOS process, targeting output frequencies up to 10 GHz, and is evaluated across process, voltage, and temperature (PVT) variations.