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collection Anno Titolo Autore file(s)
Lauree Magistrali 2021/2022 Analysis and Design of Capacitively Coupled Level Shifter Architectures for Motor Control PWM Applications CANATO, LUCA
Lauree Magistrali 2018/2019 ASYNCHRONOUS LOW-POWER TRANSMISSION OF DIGITAL SIGNALS BETWEEN DIFFERENT VOLTAGE DOMAINS FOR APPLICATIONS IN HV GATE DRIVERS REALIZED IN SOI TECHNOLOGY PAGANINI, AMEDEO CARLO
Lauree Magistrali 2022/2023 Characterization and Design Improvements of Non-Volatile Memory in BCD Technology COLOMBO, MASSIMILIANO
Lauree Magistrali 2024/2025 Design and characterization of an integrated junction temperature sensor for SiC power MOSFETs with one-wire interface VALDRIGHI, PAOLO
Lauree Magistrali 2022/2023 Design di un circuito di identificazione dei fault per la protezione dei power switches nei sistemi di controllo motore PWM BRUNOLDI, LUCA
Lauree Magistrali 2018/2019 Design of a Parallel Interface Generator for SoC Digital Communication Protocols LUZZATI, ANDREA
Lauree Magistrali 2022/2023 Design of a Programmable Word Line Voltage Regulator for Analog in Memory Computing based on PCM Arrays BOZKURT, BERK
Lauree Magistrali 2020/2021 Design of an Analog to Digital Converter for Analog in Memory Computing VIGNALI, RICCARDO
Lauree Magistrali 2020/2021 ENERGY HARVESTING SYSTEMS FOR IoT DEVICES: MODELLING AND DESIG ZUCCHELLI, ANDREA FRANCESCO
Lauree Magistrali 2024/2025 Experimental analysis of an hardware accelerator for AI algorithms based on PCM devices FERRARI, FILIPPO MARIA
Lauree Magistrali 2020/2021 Experimental Analysis of Programming characteristic of Phase-Change Memory cells ABUHADRA, MOHAMED DIA ELDDIN SADIQ
Lauree Magistrali 2020/2021 High Precision Self-Calibrating Bandgap Voltage Reference with Curvature Compensation GATTI, MARCO
Lauree Magistrali 2023/2024 High speed PWM DAC design for Analog In Memory Computing Mixed Signal IP ROVERSELLI, LUCA
Lauree Magistrali 2021/2022 Integrated Gate Driver for Very Low-Voltage-Driven Power Switch SETTI, FRANCESCO
Lauree Magistrali 2019/2020 Integrated Load Current Sensor for High Frequency Buck Switching Converter CARDELLI, GABRIELE MARIA
Lauree Magistrali 2023/2024 LDO DESIGN IN NANOSCALE FINFET TECHNOLOGY FOR LOW POWER SOC CARDONE, CARMEN LAURA
Lauree Magistrali 2021/2022 Logic Synthesis of a Low Power Digital ARM-based SoC CAIULO, ANDREA
Lauree Magistrali 2019/2020 Model of an advanced digital control loop for DC-DC converter IANNELLI, LUCA
Lauree Magistrali 2014/2015 Modeling of crosspoint spin-transfer torque random access memory array ATTRAMINI, MICHELE
Lauree Magistrali 2022/2023 MODELLO COMPORTAMENTALE DI UN LOOP DI CONTROLLO DIGITALE PER CONVERTITORI DC-DC BASATO SU RETE NEURALE NANDIALATH RADHAKRISHNAN, SANDEEP KRISHNAN
Mostrati risultati da 1 a 20 di 25
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